1 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) nm25c040 4k-bit serial cmos eeprom (serial peripheral interface (spi) synchronous bus) general description the nm25c040 is a 4096-bit cmos eeprom with an spi compatible serial interface. the nm25c040 is designed for data storage in applications requiring both non-volatile memory and in- system data updates. this eeprom is well suited for applications using the 68hc11 series of microcontrollers that support the spi interface for high speed communication with peripheral devices via a serial bus to reduce pin count. the nm25c040 is imple- mented in fairchild semiconductors floating gate cmos process that provides superior endurance and data retention. the serial data transmission of this device requires four signal lines to control the device operation: chip select (cs), clock (sck), data in (si), and serial data out (so). all programming cycles are completely self-timed and do not require an erase before write. block write protection is provided by programming the sta- tus register with one of four levels of write protection. additionally, separate write enable and write disable instruc- tions are provided for data protection. hardware data protection is provided by the wp pin to protect against inadvertent programming. the hold pin allows the serial communication to be suspended without resetting the serial sequence. block diagram march 1999 features n 2.1 mhz clock rate @ 2.7v to 5.5v n 4096 bits organized as 512 x 8 n multiple chips on the same 3-wire bus with separate chip select lines n self-timed programming cycle n simultaneous programming of 1 to 4 bytes at a time n status register can be polled during programming to monitor ready/busy n write protect (wp) pin and write disable instruction for both hardware and software write protection n block write protect feature to protect against accidental writes n endurance: 1,000,000 data changes n data retention greater than 40 years n packages available: 8-pin dip, 8-pin so, or 8-pin tssop ds012401-1 ? 1999 fairchild semiconductor corporation instruction decoder control logic and clock generators high voltage generator and program timer instruction register program enable data in/out register 8 bits data out buffer non-volatile status register decoder 1 of 512 address counter/ register eeprom array 4096 bits (512 x 8) read/write amps cs hold sck v cc v ss v pp wp si so
2 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) connection diagram dual-in-line package (n), so package (m8), and tssop package (mt8) top view see package number n08e (n), m08a (m8), and mtc08 (mt8) pin names cs chip select input so serial data output wp write protect v ss ground si serial data input sck serial clock input hold suspends serial data v cc power supply ordering information nm 25 c xx lz e xx letter description package n 8-pin dip m8 8-pin so mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current density/mode 040 4k, mode 0 c cmos technology w total array write protect interface 25 spi nm fairchild nonvolatile memory prefix cs so wp v ss v cc hold sck si 8 7 6 5 1 2 3 4 nm25c040 ds012401-2
3 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) standard voltage 4.5 v cc 5.5v specifications absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm25c040 0 c to +70 c nm25c040e -40 c to +85 c nm25c040v -40 c to +125 c power supply (v cc ) 4.5v to 5.5v dc and ac electrical characteristics 4.5v v cc 5.5v (unless otherwise specified) symbol parameter conditions min max units i cc operating current cs = v il 3ma i ccsb standby current cs = v cc 50 m a i il input leakage v in = 0 to v cc -1 +1 m a i ol output leakage v out = gnd to v cc -1 +1 m a v il cmos input low voltage -0.3 v cc * 0.3 v v ih cmos input high voltage 0.7 * v cc v cc + 0.3 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = -0.8 ma v cc - 0.8 v f op sck frequency 2.1 mhz t ri input rise time 2.0 m s t fi input fall time 2.0 m s t clh clock high time (note 2) 190 ns t cll clock low time (note 2) 190 ns t csh min cs high time (note 3) 240 ns t css cs setup time 240 ns t dis data setup time 100 ns t hds hold setup time 90 ns t csn cs hold time 240 ns t din data hold time 100 ns t hdn hold hold time 90 ns t pd output delay c l = 200 pf 240 ns t dh output hold time 0 ns t lz hold to output low z 100 ns t df output disable time c l = 200 pf 240 ns t hz hold to output high z 100 ns t wp write cycle time 1C4 bytes 10 ms capacitance t a = 25 c, f = 2.1/1 mhz (note 4) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf ac test conditions output load c l = 200 pf input pulse levels 0.1 * v cc C 0.9 * v cc timing measurement reference level 0.3 * v cc - .07 * v cc note 1: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: the f op frequency specification specifies a minimum clock period of 1/f op . therefore, for every f op clock cycle, t clh + t cll must be equal to or greater than 1/f op . for example, if the 2.1mhz period = 476ns and t clh = 190ns, t cll must be 286ns. note 3: cs must be brought high for a minimum of t csh between consecutive instruction cycles. note 4: this parameter is periodically sampled and not 100% tested.
4 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) low voltage 2.7v v cc 4.5v specifications absolute maximum ratings (note 5) ambient storage temperature -65 c to +150 c all input or output voltage with respect to ground +6.5v to -0.3v lead temp. (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature nm25c040l/lz 0 c to +70 c nm25c040le/lze -40 c to +85 c nm25c040lv -40 c to +125 c power supply (v cc ) 2.7vC4.5v dc and ac electrical characteristics 2.7v v cc 4.5v (unless otherwise specified) 25c040l/le 25c040lv 25c040lz/ze symbol parameter part conditions min. max. min max units i cc operating current cs = v il 33ma i ccsb standby current l cs = v cc 10 10 m a lz 1 n/a m a i il input leakage v in = 0 to v cc -1 1 -1 1 m a i ol output leakage v out = gnd to v cc -1 1 -1 1 m a v il input low voltage -0.3 v cc * 0.3 -0.3 v cc * 0.3 v v ih input high voltage v cc * 0.7 v cc + 0.3 v cc * 0.7 v cc + 0.3 v v ol output low voltage i ol = 0.8 ma 0.4 0.4 v v oh output high voltage i oh = C0.8 ma v cc - 0.8 v cc - 0.8 v f op sck frequency 1.0 1.0 mhz t ri input rise time 2.0 2.0 m s t fi input fall time 2.0 2.0 m s t clh clock high time (note 6) 410 410 ns t cll clock low time (note 6) 410 410 ns t csh min. cs high time (note 7) 500 500 ns t css cs setup time 500 500 ns t dis data setup time 100 100 ns t hds hold setup time 240 240 ns t csn cs hold time 500 500 ns t din data hold time 100 100 ns t hdn hold hold time 240 240 ns t pd output delay c l = 200 pf 500 500 ns t dh output hold time 0 0 ns t lz hold output low z 240 240 ns t df output disable time c l = 200 pf 500 500 ns t hz hold to output hi z 240 240 ns t wp write cycle time 1-4 bytes 15 15 ms capacitance t a = 25 c, f = 2.1/1 mhz (note 8) symbol test typ max units c out output capacitance 3 8 pf c in input capacitance 2 6 pf ac test conditions output load c l = 200pf input pulse levels 0.1 * v cc - 0.9 * v cc timing measurement reference level 0.3 * v cc - 0.7 * v cc note 5: stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposur e to absolute maximum rating conditions for extended periods may affect device reliability. note 6: the f op frequency specification specifies a minimum clock period of 1/f op . therefore, for every f op clock cycle, t clh + t cll must be equal to or greater than 1/f op . for example, if the 2.1mhz period = 476ns and t clh = 190ns, t cll must be 286ns. note 7: cs must be brought high for a minimum of t csh between consecutive instruction cycles. note 8: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) ac test conditions (continued) figure 1. synchronous data timing diagram si so sck cs data out (mosi) data in (miso) serial clock (clk) ss0 ss1 ss2 ss3 si so sck cs si so sck cs si so sck cs spi chip selection master mcu nm25c040 ds012401-3 ds012401-4 figure 3. spi serial interface cs sck si so v ih v il v ih v il v ih v il v oh v ol t css t csh t csn t dis t pd t dh t df t din t clh t cll sck hold so t hz t hdn t hds t hdn t hds t lz figure 2. hold timing ds012401-6
6 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description table 1. instruction set instruction instruction operation name opcode wren 00000110 set write enable latch wrdi 00000100 reset write enable latch rdsr 00000101 read status register wrsr 00000001 write status register read 0000a011 read data from memory array write 0000a010 write data to memory array note: as the nm25c040 requires 9 address bits (4,096 ? 8 = 512 bytes = 2 9 ), the 9th bit (for r/w instructions) is inputted in the instruction set byte in bit i 3 . this convention only applies to 4k spi protocol. master : the device that generates the serial clock is desig- nated as the master. the nm25c040 can never function as a master. slave : the nm25c040 always operates as a slave as the serial clock pin is always an input. transmitter/receiver : the nm25c040 has separate pins for data transmission (so) and reception (si). msb : the most significant bit is the first bit transmitted and received. chip select : the chip is selected when pin cs is low. when the chip is not selected, data will not be accepted from pin si, and the output pin so is in high impedance. serial op-code : the first byte transmitted after the chip is selected with cs going low contains the op-code that defines the operation to be performed. protocol : when connected to the spi port of a 68hc11 microcontroller, the nm25c040 accepts a clock phase of 0 and a clock polarity of 0. the spi protocol for this device defines the byte transmitted on the si and so data lines for proper chip operation. see figure 4. hold : the hold pin is used in conjunction with the cs to select the device. once the device is selected and a serial sequence is underway, hold may be forced low to suspend further serial communication with the device without resetting the serial se- quence. note that hold must be brought low while the sck pin is low. the device must remain selected during this sequence. to resume serial communication hold is brought high while the sck pin is low. the so pin is at a high impedance state during hold. invalid op-code : after an invalid code is received, no data is shifted into the nm25c040, and the so data output pin remains high impedance until a new cs falling edge reinitializes the serial communication. see figure 5. figure 5. invalid op-code cs si so invalid code ds012401-7 cs sck si so bit 7 bit 6 bit 0 bit 1 bit 7 bit 0 ds012401-5 figure 4. spi protocol data is clocked in on the positive sck edge and out on the negative sck edge.
7 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) functional description (continued) read sequence: reading the memory via the serial spi link requires the following sequence. the cs line is pulled low to select the device. the read op-code (which includes a8) is transmitted on the si line followed by the byte address (a7Ca0) to be read. after this is done, data on the si line becomes dont care. the data (d7Cd0) at the address specified is then shifted out on the so line. if only one byte is to be read, the cs line can be pulled back to the high level. it is possible to continue the read sequence as the byte adress is automatically incremented and data will continue to be shifted out. when the highest address is reached (1ff), the address counter rolls over to lowest address (000) allowing the entire memory to be read in one continuous read cycle. see figure 6. level status register bits array address bp1 bp0 protected 0 0 0 none 1 0 1 180-1ff 2 1 0 100-1ff 3 1 1 000-1ff write enable (wren) : when v cc is applied to the chip, it powers up in the write disable state. therefore, all programming modes must be preceded by a write enable (wren) instruc- tion. at the completion of a write or wrsr cycle the device is automatically returned to the write disable state. note that a write disable (wrdi) instruction will also return the device to the write disable state. see figure 8. figure 8. write enable cs si so wren op-code ds012401-10 write disable (wrdi) : to protect against accidental data disturbance the write disable (wrdi) instruction disables all programming modes. see figure 9. figure 9. write disable cs si so wrdi op-code ds012401-11 table 3. block write protection levels figure 6. read sequence figure 7. read status cs si so read op-code byte addr. data n data n+1 data n+2 data n+3 cs si so rdsr op-code sr data msblsb ds012401-8 ds012401-9 read status register (rdsr) : the read status register (rdsr) instruction provides access to the status register is used to interrogate the ready/busy and write enable status of the chip. two non-volatile status register bits are used to select one of four levels of block write protection. the status register format is shown in table 2. table 2. status register format bit bit bit bit bit bit bit bit 76543210 x x x x bp1 bp0 wen rdy x = don't care. status register bit 0 = 0 (rdy) indicates that the device is ready; bit 0 = 1 indicates that a program cycle is in progress. bit 1 = 0 (wen) indicates that the device is not write enabled; bit 1 = 1 indicates that the device is write enabled. non-volatile status register bits 2 and 3 (bp0 and bp1) indicate the level of block write protection selected. the block write protec- tion levels and corresponding status register control bits are shown in table 3. note that if a rdsr instruction is executed during a programming cycle only the rdy bit is valid. all other bits are 1s. see figure 7. write sequence : to program the device, the write pro- tect (wp) pin must be held high and two separate instructions must be executed. the chip must first be write enabled via the write enable instruction and then a write instruction must be executed. moreover, the address of the memory location(s) to be programmed must be outside the protected address field selected by the block write protection level. see table 3. a write command requires the following sequence. the cs line is pulled low to select the device, then the write op-code (which includes a8) is transmitted on the si line followed by the high order address byte (a10-a8) and the byte address(a7Ca0) and the corresponding data (d7-d0) to be written. programming will start after the cs pin is forced back to a high level. note that the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 data bit. see figure 10.
8 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) sck si so cs d0 d1 d2 ds012401-12 functional description (continued) figure 10. write sequence the ready/busy status of the device can be determined by executing a read status register (rdsr) instruction. bit 0 = 1 indicates that the write cycle is still in progress and bit 0 = 0 indicates that the write cycle has ended. during the write programming cycle (bit 0 = 1) only the read status regis- ter instruction is enabled. the nm25c040 is capable of a 4 byte page write operation. after receipt of each byte of data the two low order address bits are internally incremented by one. the seven high order bits of the address will remain constant. if the master should transmit more than 4 bytes of data, the address counter will roll over, and the previously loaded data will be reloaded. see figure 11. the wrsr command requires the following sequence. the cs line is pulled low to select the device and then the wrsr op-code is transmitted on the si line followed by the data to be pro- grammed. see figure 12. cs si so write op-code byte addr (n) data (n) data (n + 1) data (n + 2) data (n + 3) cs si so wrsr op-code sr data xxxxbp1bp0xx ds012401-13 ds012401-14 figure 11. 4 byte page write figure 12. write status register bp0 sck si so cs ds012401-15 figure 13. start wrsr condition at the completion of a write cycle the device is automatically returned to the write disable state. if the device is not write enabled, the device will ignore the write instruction and return to the standby state when cs is forced high. a new cs falling edge is required to re-initialize the serial communication. write status register (wrsr): the write status register (wrsr) instruction is used to program the non- volatile status register bits 2 and 3 (bp0 and bp1). the write protect (wp) pin must be held high and two separate instruc- tions must be executed. the chip must first be write enabled via the write enable instruction and then a wrsr instruction must be executed. note that the first four bits are dont care bits followed by bp1 and bp0 then two additional dont care bits. programming will start after the cs pin is forced back to a high level. as in the write instruction the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the last dont care bit. see figure 13. the ready/busy status of the device can be determined by executing a read status register (rdsr) instruction. bit 0 = 1 indicates that the wrsr cycle is still in progress and bit 0 = 0 indicates that the wrsr cycle has ended. at the completion of a write cycle the device is automatically returned to the write disable state.
9 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) molded small out-line package (m8) package number m08a molded dual-in-line package (n) package number n08e 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) 0.010 (0.254) max. lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ typ 0.008 (0.203) 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.008 - 0.010 (0.203 - 0.254) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 30 typ. physical dimensions inches (millimeters) unless otherwise noted 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident
10 www.fairchildsemi.com nm25c040 rev. d.1 nm25c040 4k-bit serial cmos eeprom (serial periphrial interface (spi) synchronous bus) 8-pin molded tssop, jedec (mt8) package number mtc08 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.50) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. max 0.0433 (1.1) 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 [0.50 - 0.70] 0.0075 - 0.0098 [0.19 - 0.25] seating plane gage plane see detail a land pattern recommendation detail a typ. scale: 40x physical dimensions inches (millimeters) unless otherwise noted note: metal mask option for 16-byte page size. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841
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